On this page · 12 sections
- What changed in 2026: Venice launched, Diamond Rapids moved to 2027
- Diamond Rapids: what Intel has confirmed and what is still unknown
- EPYC 9006 Venice: what AMD sells now
- Head-to-head: flagship Diamond Rapids vs flagship Venice
- Licensing: core count, not socket count, drives the software bill
- Worked example: when 256 cores raise your licence bill
- Power, memory and platform longevity
- Decision table: refresh now or wait for Diamond Rapids
- India, EU and US notes
- Refresh checklist
- How eCorpIT can help
- References
Summary. Diamond Rapids is real, but you cannot buy it yet. On 29 October 2026 Intel said its first Intel 18A-P server processor is sampling and on track to ramp in 2027, with Oracle planning OCI X14 instances on it. At Hot Chips in August, Intel described up to 256 cores, 1.28 GB of last-level cache, 16 memory channels at up to 12,800 MT/s and 128 lanes of PCIe Gen 6. It has published no SKU list, power rating, price or launch date, and ServeTheHome reports Intel said Diamond Rapids will not support Hyper-Threading. AMD launched its EPYC 9006 family, Venice, on 23 July 2026, with up to 256 cores and 512 threads, the same memory ceiling, PCIe Gen 6 and a 600 W top part. The flagships tie on cores and memory; they differ on threads, power, timing and roadmap. Per-core software is the bigger cost: Windows Server 2025 Datacenter lists at $6,771 per 16 cores, and VMware VCF needs a licence for every physical core, so a two-socket 256-core server is 512 licensed cores on either vendor. Our verdict: if hardware leaves support before late 2027, refresh on EPYC 9006 or Xeon 6 now and size cores to the licence bill. Wait for Diamond Rapids only if Intel accelerators, ISV certification or OCI X14 tie you to it.
About this article. For infrastructure owners and finance teams planning a 2027 server refresh. On 7 November 2026 we checked roadmap and specification claims against Intel and AMD primary material (earnings remarks, press releases, Hot Chips slides, specification pages, a white paper) and licence prices against Microsoft and Broadcom. AMD's product page and white paper refused automated access, so we read archived copies from 11 and 12 October 2026. Third-party reporting is attributed by name; leaked specifications are left out. We have not benchmarked either processor. This is not licensing or financial advice, vendors change prices, and no vendor paid for inclusion. Researched with AI assistance and reviewed by our editorial team.
What changed in 2026: Venice launched, Diamond Rapids moved to 2027
Intel set 2027 at Computex. ServeTheHome reports that Intel's June 2026 Computex roadmap labelled Diamond Rapids as Xeon 7, placed it in 2027 on Intel 18A-P, and promised roughly 50% more cores than Xeon 6 with double the memory bandwidth. Intel also said there that Diamond Rapids will not support Hyper-Threading, which it expects to return with the next generation, Coral Rapids. Intel's own Hot Chips slides do not mention Hyper-Threading.
Intel showed the architecture at Hot Chips. On 24 August 2026 Intel presented compute building blocks of core chiplets with up to 16 cores each, stacked on base tiles holding a shared last-level cache, plus two Fabric Hub tiles for memory, I/O and accelerators. The flagship combines four building blocks for up to 256 cores. ServeTheHome reads the 256-core configuration as a recent roadmap addition to match AMD.
Intel confirmed sampling. In its third-quarter remarks on 29 October, Intel said Diamond Rapids is sampling with strong customer interest for inference and agentic work, that Clearwater Forest (sold as Xeon 6+) is shipping for revenue, and that it expects the industry to stay supply-constrained through 2027 and into 2028. It also forecast industry server CPU units to grow more than 30% in both 2026 and 2027. Two days earlier, Intel and Oracle announced planned OCI X14 instances on Diamond Rapids.
AMD launched Venice. AMD announced the production ramp of 6th Gen EPYC on TSMC 2nm in Taiwan on 21 May, with plans to add TSMC Arizona, launched the EPYC 9006 family at Advancing AI on 23 July, and said on 3 November that it expects growth to accelerate in the fourth quarter as it scales Venice and Helios production. AMD and Oracle said on 27 October that upcoming OCI Compute E7 instances will run on 6th Gen EPYC.
Diamond Rapids: what Intel has confirmed and what is still unknown
Presented figures come from Intel's Hot Chips post and keynote handout, timing and cloud plans from Intel's October announcements, and the Hyper-Threading item from ServeTheHome.
| Item | Detail | Status |
|---|---|---|
| Timing | Sampling; on track to ramp in 2027 | Intel, 29 October 2026 |
| Launch window | Second half of 2027 | ServeTheHome expectation, not Intel |
| Process | Intel 18A-P | Intel |
| Cores | Up to 256, from four compute building blocks | Presented; no SKUs announced |
| Threads | No Hyper-Threading, so 256 threads at 256 cores | Intel at Computex, as reported |
| Last-level cache | Up to 1.28 GB | Presented |
| Memory | 16 channels; DDR5-8000 or MRDIMM-12800; up to 1.6 TB/s | Presented |
| I/O | 128 lanes usable as PCIe Gen 6, CXL 3.0 or UPI 3, plus 8 lanes of PCIe Gen 4 | Presented |
| Accelerators and instructions | QAT, DSA and IAA in each Fabric Hub; AMX with FP8, FP16 and BF16; AVX10.2; APX | Presented |
| Power, SKUs, price, socket | Not published | Unknown |
| Cloud | Planned OCI X14 instances | Intel and Oracle, 27 October 2026 |
Two points matter for buyers. The 256-core figure is the top of a presented design, not a shipping SKU. And Intel has described only the 16-channel flagship, so until it says otherwise its options for smaller servers in 2027 are Xeon 6 and Xeon 6+.
EPYC 9006 Venice: what AMD sells now
AMD splits 6th Gen EPYC into four lines. Power comes from AMD's SKU tables, which use Default CPU Power in place of TDP, and memory details from AMD's white paper.
| Line | Cores and threads | Default CPU Power | Memory and I/O | Built for |
|---|---|---|---|---|
| EPYC 9006 SP7 | 64 to 256 cores, up to 512 threads; up to 96 cores at 5 GHz | 300 W to 600 W; five of nine listed SKUs at 500 W | 16 channels DDR5, MRDIMM up to 12,800 MT/s, about 1.6 TB/s and up to 4 TB per socket; PCIe Gen 6, CXL 3.1 | Density, VMs, agent sandboxes, AI host nodes |
| EPYC 9006 SP8 | 8 to 128 cores, up to 256 threads | 130 W to 400 W | Smaller platform; AMD lists 16 channels only for select 9006 parts | Enterprise, edge, power-limited racks |
| EPYC 9006X SP7 | High-cache variant, up to 5.15 GHz, 3x the L3 per core of 9006 SP7 | Not stated | As SP7 | HPC and memory-sensitive work |
| EPYC 9006 LP | Formerly Verano | Not stated | LPDDR memory, up to 5 GHz | AI host CPU in rack-scale systems |
The flagship EPYC 9996 has 256 cores, 512 threads and 1,024 MB of L3, with a default of 600 W and a configurable range of 400 W to 600 W. AMD's launch footnotes model a 256-core part at 400 W, the bottom of that range, so plan rack power on 600 W per socket until your OEM confirms the configuration. AMD's product page carries no prices, so expect quotes; Intel publishes recommended customer prices, such as $13,955 for the 128-core Xeon 6980P.
Head-to-head: flagship Diamond Rapids vs flagship Venice
Sources are as for the two tables above, plus AMD's July roadmap announcement.
| Specification | Intel Diamond Rapids (presented) | AMD EPYC 9006 SP7 Venice |
|---|---|---|
| Status on 7 November 2026 | Sampling; ramp in 2027 | Launched 23 July 2026; production scaling |
| Process | Intel 18A-P, Intel fabs | TSMC 2nm; Arizona ramp planned |
| Maximum cores | 256 (presented) | 256 |
| Maximum threads | 256 (no Hyper-Threading, as reported) | 512 (SMT) |
| Memory | 16 channels; DDR5-8000 or MRDIMM-12800; up to 1.6 TB/s | 16 channels; MRDIMM up to 12,800 MT/s; about 1.6 TB/s |
| PCIe and CXL | 128 lanes Gen 6; CXL 3.0 | Gen 6; CXL 3.1 |
| Top-SKU power | Not published | 600 W default |
| Built-in acceleration | QAT, DSA and IAA engines; AMX | AVX-512; no offload engines listed in AMD's material |
| Smaller sibling for 2027 | None described | EPYC 9006 SP8, 8 to 128 cores |
| Next generation | Coral Rapids, Hyper-Threading returns (reported); no date | Zen 7 Florence, Ferrara and Fidenza in 2028; sockets not disclosed |
| Named cloud instances | OCI X14 (planned) | OCI Compute E7 (upcoming) |
Both bandwidth figures follow from 16 channels × 12,800 MT/s × 8 bytes, about 1.6 TB/s per socket. Nothing here tells you which chip is faster on your workload. Intel has published no Diamond Rapids benchmarks, and AMD labels its claim of up to 3.3x the rack-level throughput of NVIDIA Vera for the EPYC 9996, inside a 100 kW budget, as a projection. Our July Venice analysis explains why such figures are modelled, not measured.
Licensing: core count, not socket count, drives the software bill
For most enterprise estates, per-core software costs more than the CPU. Two Xeon 6980P processors have a combined recommended customer price of 2 × $13,955 = $27,910, while licensing their 256 cores for Windows Server Datacenter at list costs 16 × $6,771 = $108,336. How the two main per-core licences work:
- Windows Server 2025. Microsoft's suggested prices are $1,176 for Standard and $6,771 for Datacenter, each covering 16 core licences. Pay-as-you-go through Azure Arc costs $33.58 per core per month.
- VMware VCF and VVF. Broadcom's KB 313548 bases licensing on the total number of physical CPU cores, with a minimum of 16 cores per CPU, and requires licences for every physical core on each CPU that runs the software. Broadcom publishes no list price.
Three consequences follow:
- Every physical core costs money, whether you use it or not. A two-socket server with two 256-core CPUs is 512 licensed cores on either vendor.
- Threads are not counted under these core-based models. Venice exposes 512 threads on 256 licensed cores; Diamond Rapids, as reported, 256. Whether SMT helps depends on the workload. AMD's white paper notes that some deployments turn SMT off for stronger isolation, more predictable latency or licensing compliance, so check whether any of your software counts threads.
- Consolidation saves licences only if total licensed cores fall. AMD argues that fewer, denser servers cut per-core software costs, a benefit it says does not apply in the same way to per-user or per-device licences. It holds only when the new estate has fewer physical cores than the old one.
The table applies Microsoft's $6,771 Datacenter list price.
| Two-socket host configuration | Licensed cores | Datacenter 16-core packs | List cost per host |
|---|---|---|---|
| 2 × 32 cores | 64 | 4 | $27,084 |
| 2 × 64 cores | 128 | 8 | $54,168 |
| 2 × 128 cores | 256 | 16 | $108,336 |
| 2 × 256 cores | 512 | 32 | $216,672 |
The licence bill scales linearly with cores. Choosing a CPU is really choosing how much work each licensed core does.
Worked example: when 256 cores raise your licence bill
Take an estate of 20 two-socket hosts with 24 cores per socket, all running Windows Server Datacenter: 20 × 48 = 960 licensed cores, or 60 packs × $6,771 = $406,260 at list. Assume each new core does twice the work of an old one. That is our assumption, not a vendor claim; verify it with your own benchmark. You then need about 480 cores of capacity, plus one spare host for N+1 failover. In this model every host, including the spare, is licensed.
| Option | Hosts (capacity + spare) | Licensed cores | 16-core packs | Datacenter list cost |
|---|---|---|---|---|
| Today: 2 × 24 cores | 20 | 960 | 60 | $406,260 |
| A. 2 × 32 cores | 8 + 1 = 9 | 576 | 36 | $243,756 |
| B. 2 × 64 cores | 4 + 1 = 5 | 640 | 40 | $270,840 |
| C. 1 × 256 cores | 2 + 1 = 3 | 768 | 48 | $325,008 |
| D. 2 × 256 cores | 1 + 1 = 2 | 1,024 | 64 | $433,344 |
Capacity hosts are 480 divided by cores per host, rounded up. The densest option costs the most because the spare host alone carries 512 licensed cores. For a small or mid-sized estate, 32-core and 64-core parts usually minimise licences. The 256-core flagships pay off in large clusters, where N+1 overhead is a small fraction of the total, and in VM-dense or agent-sandbox work where threads per licensed core matter. VCF follows the same arithmetic at your quoted per-core price; our VCF 9 upgrade guide covers the counting rules.
Power, memory and platform longevity
Power per socket keeps rising. On AMD's SKU tables, EPYC 9006 SP7 parts default to 300 W to 600 W, with five of nine at 500 W, and SP8 parts to 130 W to 400 W. Intel lists the 128-core Xeon 6980P at 500 W and the 288-core Xeon 6+ 6990E+ at 450 W, with a 330 W profile, 12 DDR5 channels and 96 PCIe Gen 5 lanes. Intel has not rated Diamond Rapids. Two 600 W CPUs are 1.2 kW per node before memory, drives and NICs, so check rack power and cooling before choosing the top SKU.
Memory may cost more than the CPU. Filling 16 channels on two sockets takes at least 32 DIMMs. AMD's own white paper says DRAM became a large share of server bill-of-materials cost in mid-2026, TrendForce expects DRAM supply to stay tight through 2027, and Intel's CEO listed an unprecedented memory shortage among its near-term challenges on 29 October. Smaller platforms with fewer DIMMs, such as EPYC 9006 SP8 or Xeon 6, can make more financial sense than either 16-channel flagship. Our piece on the 2027 server memory squeeze covers pricing.
Neither vendor has committed a socket for its next generation. AMD says its Zen 7 EPYC processors, Florence, Ferrara and Fidenza, arrive in 2028, but has not said which sockets they use. A CPU-only upgrade for Venice boards is therefore unconfirmed and would also depend on your OEM's BIOS and power delivery, so get any commitment in writing. Intel's Xeon 6 and 6+ top out at 12 memory channels and PCIe Gen 5, while Diamond Rapids moves to 16 channels and PCIe Gen 6, so plan on new platforms. Intel has published no socket details and has not said whether Coral Rapids will share the Diamond Rapids platform.
Software portability is improving. On 20 October AMD and Intel agreed to combine their x86 PyTorch optimisation work in oneDNN, which reduces the risk of tuning AI pre- and post-processing for one x86 vendor. Intel's AMX, QAT and IAA still need code that targets them, so test before you switch.
Decision table: refresh now or wait for Diamond Rapids
| Your situation | Recommendation | Why |
|---|---|---|
| Hardware leaves support before late 2027 | Refresh now on EPYC 9006, Xeon 6 or Xeon 6+ | Diamond Rapids ramps in 2027 with no SKU list or ship date |
| Small estate under about 10 hosts | Avoid 256-core parts; pick 32 to 64 cores | N+1 spare hosts multiply licensed cores |
| Per-core licences dominate (Windows Datacenter, VCF) | Size cores to the licence budget first | Licence cost scales linearly with physical cores |
| VM-dense, container or agent-sandbox estate | EPYC 9006 SP7 | 512 threads per 256 licensed cores |
| Heavy use of QAT, AMX or IAA, or ISV certified only on Xeon | Xeon 6 now; pilot Diamond Rapids once Intel publishes SKUs | Avoids porting accelerator code |
| Power-capped racks | EPYC 9006 SP8 or Xeon 6+ in its lower-power profile | Most SP7 parts default to 500 W or more |
| Want a CPU-only upgrade in 2028 | Get a written OEM commitment before relying on one | Neither vendor has published next-generation sockets |
| Renting rather than buying | OCI E7 when available; evaluate OCI X14 at launch | Both announced; no public pricing yet |
India, EU and US notes
India. Neither vendor publishes rupee pricing, and memory is the biggest swing in local quotes. Windows Server 2016 extended support ends on 12 January 2027, so plan the operating system and hardware refresh together. Given Intel's warning that supply stays tight into 2028, ask OEMs for committed delivery dates before you sign.
EU. Higher socket power meets tighter efficiency rules. If you operate in Germany, read our note on the German data centre renewable energy rule before sizing new halls.
US. Intel is ramping 18A in Oregon and Arizona, and says Diamond Rapids is built exclusively on Intel technology. AMD plans to ramp Venice at TSMC Arizona. Buyers with domestic-sourcing rules should confirm the fab of origin for each SKU.
Refresh checklist
- Inventory every per-core licence (Windows Server, VCF or VVF, databases) and its renewal date.
- Benchmark your own workloads on EPYC 9006 and Xeon 6 samples, not vendor multipliers.
- Model licensed cores including N+1 spares, for at least three core counts.
- Confirm rack power and cooling for 500 W to 600 W sockets.
- Price memory separately; it may decide between 16-channel and smaller platforms.
- Get written OEM commitments on next-generation CPU support for the board you buy.
- If Intel accelerators matter, request Diamond Rapids samples and a delivery quarter in writing, and lock allocation early.
How eCorpIT can help
eCorpIT is a Gurugram-based technology organisation, founded in 2021, assessed at CMMI Level 5 and MSME certified, with senior-led engineering teams working across AWS, Microsoft and Google platforms. Our data centre and cloud networking team helps infrastructure owners plan server refreshes around licensed-core models, rack power and cooling, and rent-versus-buy options. Talk to us at /contact-us/.
Last updated: 7 November 2026.
